Development of conductive adhesive materials for via fill applications

Abstract

As mobile computing and telecommunication electronics are spreading fast, a demand for microelectronics packaging schemes for high density, fine pitch, high performance and low cost becomes even more severe. Specifically, the conventional printed circuit board (PCB) with plated-through-hole (PTH) vias is difficult to justify its manufacturing cost as well as the packaging density requirement. To meet this challenge, several new manufacturing schemes of high density and high performance PCB have been recently introduced such as surface laminar circuit (SLC), array layer inner via hole (ALIVH) and others. This new PCB fabrication process is categorized as sequential build-up (SBU) or build-up multilayer (BUM) using laminate-based substrates, where via holes are filled with a conductive paste material to make reliable vertical or Z-interconnects. In this paper, a new electrically conducting paste material to be used for via filling is introduced. The new conducting material consists of a conducting filler powder coated with a low melting point metal or alloy, a mixture of several thermoset resins, and other minor organic additives. By varying the filler content and resin chemistry, several formulations have been produced to fill via holes with a high aspect ratio. Via fill experiments have been performed to demonstrate void-free microstructure with good electrical continuity. Various bulk properties such as thermal, electrical and mechanical have also been characterized to understand the material behavior during via filling as well as the field service.