Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.
Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Haifeng Qian, Phillip J. Restle, et al.
IEEE TCADIS
Sophie Verdonckt-Vandebroek, Bernard S. Meyerson, et al.
IEEE Transactions on Electron Devices