Design and CAD Challenges in sub-90nm CMOS Technologies

Abstract

This paper discusses design challenges of scaled CMOS circuits in sub-90nm technologies for high-performance digital applications. To continue scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new SOI design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher Vt,lin to maintain adequate Vt,sat, continue to surface. With an eye towards the future, design and CAD issues related to sub-65nm device structures such as double gate FinFET will be discussed.