CMOS with active well bias for low-power and RF/analog applications

Abstract

We show that with a forward body bias, CMOS performance can be improved for those applications which are primarily concerned with speed, and for those which have fixed performance targets but desire lower switching energy (higher MHz/mW). Thus Vt can be set according to standby power requirement or device design (well and halo engineering), forward body bias is then applied to improve speed or to reduce active power. No compromise in Ioff results if the forward bias is applied when the circuits are active, during which time Ioff and the leakage current are small compared to the switching current. Therefore a low-power CMOS strategy should use a MOSFET as a four-terminal device with a fast top gate and a slow bottom gate shared by a block. Deep-trench isolation with STI provides fine-grain isolation for body bias blocks without area penalty. Making the body available also improves the device analog properties and enables new applications. We present an active-well VCO/mixer as an example.