Buffer insertion with accurate gate and interconnect delay computation

Abstract

Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these methods use simplified interconnect and gate delay models. These models may lead to inferior solutions since the optimized objective is only an approximation for the actual delay. We propose to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm via the propagation of moments and driving point admittances up the routing tree. We have verified the effectiveness of our approach on an industry design.