Kenneth Chin, Ching-Te Chuang, et al.
IEEE Journal of Solid-State Circuits
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Kenneth Chin, Ching-Te Chuang, et al.
IEEE Journal of Solid-State Circuits
Kai-Yap Toh, Ghing-Te Chuang, et al.
IEEE Journal of Solid-State Circuits
Tze-Chiang Chen
NANO 2006
Tze-Chiang Chen, Kai-Yap Toh, et al.
IEEE Electron Device Letters