BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65nm groundrules

Abstract

This paper describes a comprehensive characterization of a 65nm, 300mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of SiCOH material and process optimization enable the minimization of damaged layers during etch and strip processes and during direct-CMP processing. Using 3D modeling the k-value of SiCOH material was shown to maintain its initial value after integration. Electrical performance, yield, reliability, and chip-to-package (CPI) evaluations are also presented. The results were comparable with conventional SiCOH integration scheme.