Attractive line codes for high-speed LANs and MANs and their realization

Abstract

Steadily increasing data rates in local and metropolitan area networks call for the high-speed realization of line codes. For many applications these line codes should be dc-free. The code selected for the Fiber Channel Standard (FCS) belongs to a class of dc-free codes known as alternate codes. New dc-free line codes that improve the timing properties of the FCS code are constructed. Look-ahead precomputation and state switching are used to reduce state computation in the feedback link of the FCS code to a single XOR operation. A high-speed encoder architecture for two-state alternate codes based on state switching and parallel processing is described using the example of the FCS code. The architecture is well-suited to VLSI implementation, because it is regular and its throughput and complexity increase linearly with the number of simultaneously processed bytes. Using this architecture the FCS code can be efficiently realized with a low-speed technology (e.g., CMOS) even at multigigabit data rates.