Analytic performance modeling for a spectrum of multithreaded processor architectures

Abstract

The throughput of pipelined processors suffers from delays associated with instruction dependencies and memory latencies. Multithreaded architectures attempt to hide such delays by sharing the processor with multiple instruction streams. In this paper we develop a comprehensive analytic framework to quantitatively evaluate the performance of a wide spectrum of mulithreaded machines, ranging from those that are capable of switching threads every cycle to those that switch threads only on long delays. The models are validated against previously published simulation and modeling results, and then used to assess the performance potential of multithreading given current processor technology.