About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
COMPEL 2017
Conference paper
Analysis and comparative evaluation of stacked-Transistor half-bridge topologies implemented with 14 nm bulk CMOS technology
Abstract
Integrated Voltage Regulators (IVRs) have become a viable solution for microprocessor's power delivery. The active parts of the most recent IVRs are built in deep-submicron CMOS technologies and use stacked transistors to allow for the use of advanced low voltage devices with superior switching performance compared to the higher voltage long-channel devices. This paper evaluates three different topologies of CMOS half-bridge converters with respect to efficiency, implementation effort, suitability for on-chip integration, and multiphase applications: The conventional half-bridge converter, the half-bridge converter with conventional Active Neutral Point Clamping (ANPC), and a halfbridge converter with a modified circuit to achieve ANPC. In-depth analysis of the transient processes during switching for all three converters, based on Cadence simulations, reveal that both half-bridge converters with ANPC achieve proper balancing of the blocking voltages of the main transistors and are capable to attain similar efficiencies of 93% at an output power of 200 mW, input and output voltages of 1.6 V and 0.8 V, respectively, and a switching frequency of 150 MHz, which is 1% higher than the one attained with the conventional half-bridge converter. Of the two ANPC half-bridge converters, however, the proposed topology allows to completely turn off its entire power stage or parts of it, features less efficiency sensitivity to variations of dead-Time, and achieves the peak efficiency at relatively higher dead-Time values. These qualities render the proposed topology particularly suitable for multiphase systems and low load operation.