SEAS: A System for Early Analysis of SoCs
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor cores, memory banks, and well-defined interfaces that are interconnected via a high-performance switch. The number of processors and memory banks are parameters that can vary depending on the application to be implemented on the chip. Applications such as protocol conversion, TCP/IP off-load engine, or firewalls can be implemented with processor counts ranging from 8 to 128. Copyright 2004 ACM.
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Nagu Dhanwada, Reinaldo A. Bergamaschi, et al.
Des Autom Embedded Syst
Christos J. Georgiou, Petros S. Stefaneas
Communications of the ACM
Christos J. Georgiou
Phoenix IPCCC 1993