Algorithms for the design verification of bipolar array chips

Abstract

A new methodology is used for the design verification of bipolar array chips. Here the authors apply analog methods to verify the logic function of the chip's basic circuits or macromodels and the noise margins. They also check for reliability by computing the current density at each device contact stud. The logic paths are implicitly verified. Several algorithms are used as building blocks in an implementation program. This includes a recursive scheduling algorithm, a Gray algorithm and an algorithm to treat differential pairs. A nonlinear Gauss-Seidel method for decoupling and solving a nonlinear set of algebraic equations is described.