Algebraic survivor memory management for Viterbi detectors

Abstract

The problem of survivor memory management of a Viterbi detector is classically solved either by a registerexchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a trace-back scheme with small power consumption, but larger latency. Here an algebraic formulation of the survivor memory management is introduced which provides a framework for the derivation of new algorithmic and architectural solutions. VLSI case studies of specific new solutions show that more than 50% savings are possible in hardware complexity as well as power consumption.