Advances in Spin-Transfer-Torque MRAM

Abstract

Spin-Transfer-Torque MRAM (STT-MRAM) is an emerging memory technology that possesses a unique combination of non-volatility, high endurance, and ease of integration using standard CMOS processing [1]. Initial applications include 1 Gb standalone memory for use as a write buffer in solid state drives, and embedded non-volatile memory for microcontroller units, as a replacement for embedded Flash. If the switching current can be reduced further, STT-MRAM could potentially be used as a replacement for SRAM in last-level-cache, providing significant system-level performance improvement due to higher density. Materials innovation lies at the heart of MRAM research, particularly for the materials used in the magnetic tunnel junction, the device used to store, read, and write data. A magnetic tunnel junction consists of metallic magnetic free and reference layers sandwiched around a thin insulating tunnel barrier. This talk will first give an overview of STT-MRAM, including how it works and the application space, and will then review the materials innovations developed at IBM for reducing the switching current. IBM has had a long history of research and development of STT-MRAM. Spin-transfer-torque switching was invented at IBM in 1996 by John Slonczewski [2], who also invented the magnetic tunnel junction [3] (which was also independently invented by Julliere [4]). High magnetoresistance using MgO tunnel barriers was first published by IBM and AIST in 2004 [5,6]. The development of perpendicularly magnetized STT-MRAM was first published by IBM and Tohoku University in 2010 [7,8]. Since then the IBM MRAM team has focused on reducing the switching current of STT-MRAM in order to enable last-level-cache applications. Key results include demonstrating reliable writing down to write-error-rates of less than 1e-11 [9], scaling down to 11 nm tunnel junctions switching in only 7.5 uA [10], and demonstrating fast reliable writing using 2 ns write pulses [11]. IBM and TDK jointly published the first demonstration of product-level yields in 2013, using an 8 Mb STT-MRAM product demonstrator [12]. Double magnetic tunnel junctions were developed to further reduce the switching current, by using two reference layers and two tunnel barriers, in order to provide torque to the free layer from both top and bottom interfaces [13]. Theory predicts that a factor of 10 reduction in switching current is possible, for perfect spin-polarization [14]. Most recently, a new device, called the double spin-torque magnetic tunnel junction was demonstrated to reduce the switching current in a similar manner, however without any penalty in the magnetoresistance, by using a low resistance non-magnetic spacer in place of the second tunnel barrier [15]. This exciting breakthrough opens up a path to using STT-MRAM as last-level-cache. [1] Andrew D. Kent and Daniel C. Worledge, Nature Nano. 10, 187 (2015) [2] J.C. Slonczewski, J. Magn. Magn. Mat., Volume 159, Issues 1–2, Pages L1-L7 (1996) [3] J. C. Slonczewski, IBM Technical Disclosure Bulletin 19, No. 6, 2331-2332 (1976) [4] M. Julliere, Physics Letters A, Volume 54, Issue 3, Pages 225-226 (1975) [5] S.S.P. Parkin et al., Nature Mater. 3, 862–867 (2004) [6] S. Yuasa, et al., Nature Mater. 3, 868–871 (2004) [7] D. C. Worledge et al., IEDM, p. 12.5.1-12.5.4 (2010) [8] Ikeda, S. et al., Nature Mater. 9, 721–724 (2010) [9] J. J. Nowak et al., IEEE Magnetics Letters, vol. 2, Art no. 3000204 (2011) [10] J. J. Nowak et al., IEEE Magnetics Letters, vol. 7, Art no. 3102604 (2016) [11] G. Hu et al., IEDM, p. 2.6.1-2.6.4 (2019) [12] Y. J. Lee et al., VLSI-TSA p1 (2013) [13] G. Hu et al., IEDM, p. 26.3.1-26.3.4 (2015) [14] D. C. Worledge, IEEE Magnetics Letters, vol. 8, Art no. 4306505 (2017) [15] G. Hu et al., IEDM, p. 2.5.1-2.5.4 (2021)