Addressable arrays implemented with one metal level for MOSFET and resistor variability characterization

Abstract

Addressable array test structures for rapid collection of statistical distributions of MOSFET parameters and parasitic resistances are described. A unique feature of these designs is that they require only one level of metal, yet are compact for placement in the scribe line for early process learning. MOSFET measurements are made over full range of I-V characteristics including leakage currents of individual devices in the sub-threshold region. A modular approach for test structure integration and parallel testability enables high efficiency in design and data acquisition.