Olivier Maher, N. Harnack, et al.
DRC 2023
This paper presents a switched-capacitor-based integer compute unit in 5nm CMOS that is designed as a drop-in replacement for an equivalent digital unit to improve power efficiency by 2. 5X. Integer multiply-accumulate (MAC) operations are recast as a scaled sum of l-b MACs, where each l-b MAC is performed using a population counter (PPCTR) circuit. Each PPCTR is an enhanced SAR ADC that performs l-b multiplication, D-A conversion, accumulation, and A-D conversion with no loss of precision. The compute unit has 4864 PPCTRs arranged as 64 processing engines, with a total throughput of 104.9 TOPS and 650 TOPS/W power efficiency for l-b MACs.
Olivier Maher, N. Harnack, et al.
DRC 2023
Tommaso Stecconi, Roberto Guido, et al.
Advanced Electronic Materials
Sae Kyu Lee, Ankur Agrawal, et al.
IEEE JSSC
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025