A novel approach to isolating the edge of the shallow trench isolation in SiGe HBTs for improved device performance

Abstract

Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT and fMAX has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX of 15/20GHz respectively. Technology computer-aided device techniques are utilized to understand the process and device changes driving the improvements in device performance observed. Three possible theories that relate to changes in the device architecture inherent to the layout variation are examined.