A multilevel copper/low-k/airgap BEOL technology

Abstract

In this publication, we show for the first time, reliable and potentially manufacturable airgap based wiring which is demonstrated on a 65nm production microprocessor. We achieve this using two techniques employing supra- and sub-lithographic templates, the latter of which uses a novel self-assembly approach. We demonstrate that multi-level airgaps can be built on the microprocessor without unduly affecting yield. Further we show that significant capacitance reductions can be obtained using these techniques. Finally we show that the microprocessor can be packaged and that the resultant modules survive the most critical packaging based reliability stresses despite the presence of airgaps at six of the uppermost wiring levels. © 2008 Materials Research Society.