Rajiv V. Joshi, Yuen Chan
ESSCIRC 2005
This paper presents a novel resonating inductor-based supply boosting scheme for low-voltage static random-access memories and logic in deep 14-nm silicon on insulator (SOI) FinFET technologies. The technique combines capacitive (C) and inductive (L) boosting for the first time. Simulation and measured hardware results from a 14-nm test chip show that this new technique is able to improve Vmin (down to 0.3 V), functional yield, and access time, when compared with designs with or without capacitive-boosted supplies. Simulations also reveal the optimal combinations of 'L' and 'C' needed for each Vdd to achieve minimal boost voltage, where the static random-access memory can be rendered fully functional in the absence of any assist circuitry. Furthermore, the resonant supply provides power savings compared with a boosted supply alone.
Rajiv V. Joshi, Yuen Chan
ESSCIRC 2005
Gouranga Charan, Jubin Hazra, et al.
DAC 2020
C.Sture Petersson, Harry J. Whitlow, et al.
Nuclear Inst. and Methods in Physics Research, B
Rajiv V. Joshi, Matt Ziegler
MIXDES 2019