A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities

Abstract

The architecture, design, and performance of a hybrid number system processor is described. The processor performs multiplication, division, square root, and square in the logarithmic number system (LNS) domain. However, the input, output, addition, and subtraction are all executed in the 32-bit IEEE standard floating-point number system. With the LNS multiplier and pipelined architecture, the processor is able to perform the geometric and complex arithmetic very effectively. The processor is also shown to compare well to an existing 32-bit floating-point DSP chip. For the same level of CMOS technology, the performance ratios between the hybrid number system and the floating-point processor are shown to be 6.4:1 and 8:1 for division and square root, respectively; for the complex FFT algorithm, the ratio is around 2:1. © 1991 IEEE.