A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology

Abstract

In this work, we demonstrate a 6.9 sq. pm embedded SRAM cell in a 0.25 pm physical design-rule salicide high-performance CMOS technology. The scalability of this salicide-CMOS embedded-SRAM technology is demonstfated by functionality of the same SRAM cell implemented in 0.35 pm and 0.25 pm design rules. To our knowledge this is the smallest reported SRAM cell in a salicide- only technology, and is achieved using deep-UV lithography, shallow-trench isolation, damascenetungsten low - resistance local interconnect, and optimization of design-rules. Process and structure studies indicate process extendability to 0.18 pm lithography generation. The CMOS technology is a 1.8 V, 0.12 pm nominal LEFP dual work-function CMOS with 4.0 nm gate oxide. The unloaded inverter and 2-way NAND gate delays are 24 and 45 ps respectively with 1.8V power supply, and 57 and 98 ps with 1.OV power supply*