A high aspect-ratio silicon substrate-via technology and applications: Through-wafer interconnects for power and ground and faraday cages for SOC isolation

Abstract

The reduction of ground inductance is crucial to the gain of RF and microwave circuits. To provide a low-inductance interconnect, we have developed a through-wafer via technology in silicon that incorporates a silicon nitride barrier liner and is filled with electroplated Cu. We have demonstrated vias with an aspect ratio as high as 14 and an inductance that approaches the theoretically expected value. Using the same technology, we have implemented a novel Faraday cage scheme for on-chip subsystem isolation that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 μm.