A Bit-Slice Architecture for Sigma-Delta Analog-ToDigital Converters

Abstract

The ∑ analog-toDigital converters are based on filtering and undersampling by the digital section of the 1-bit output stream coming from the modulator. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that both from signal processsing, as well as hardware implementation, it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It has the advantage that it can be easily expanded when higher bit resolutions are required. An application for a dual codec using only one power supply, implemented in 1.5 μm CMOS technology is given. © 1988 IEEE