A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Abstract

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44 GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2 mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8 ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1 ps at an input frequency of 40 GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30 μm x 40 μm only. © 2006, IEEE. All rights reserved.