A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential Gain in 90-nm CMOS

Abstract

A 40-Gb/s differential CMOS limiting amplifier in standard 90-nm technology is presented. The circuit dissipates as little as 80 mW from a 1 V power supply and has a differential gain of 20 dB. It can drive data at 40 Gb/s into multiple sampling circuits with a total input capacitance as high as 300 fF. The amplifier features a digitally programmable load resistor for the differential stages to control gain-peaking intensity. This can be used to cancel process variations or for active channel-compensation schemes. The output common mode voltage and circuit bias are controlled by a replica stage. The circuit occupies 0.033 mm2 of silicon real estate.