A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme

Abstract

A key challenge in high-performance I/O, as well as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range applications enables generation of arbitrary output frequencies within that range from a single choice of reference frequency. A critical challenge in fractional-N synthesizer design is the cancellation of the deterministic component of the fractional-N ΔΣ noise, allowing fractional-N solutions to be applied even in noise-sensitive contexts. In this work, we present a flexible, wide tuning range, fractional-N PLL implemented in 32nm SOI CMOS technology, introducing two separate methods - one in the proportional path and one in the integral path - to process and suppress ΔΣ noise. The demonstrated design includes an integrated automatic calibration loop to optimize noise suppression, uses a dual VCO complex to support generation of any output frequency from 13 to 28GHz from a reference clock in the range of 15 to 300 MHz, and also supports extended tuning down to 1GHz through the use of configurable output dividers.