A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS

Abstract

A 90nm CMOS 10Gb/s SerDes for chip-to-chip communications over backplanes is presented. To mitigate channel impairments, the RX uses a 5-tap DFE and the TX a 4-tap FIR filter. The IC equalization abilities are evaluated using different type of channels. The power consumption of one (TX, RX) pair and one PLL is 300mW for 1.2Vpp differential TX output swing. © 2006 IEEE.