1.6Gb/s CMOS phase-frequency locked loop for timing recovery

Abstract

A fully monolithic phase-frequency locked loop (PFLL) for timing recovery applications is implemented in a 0.25μ digital CMOS technology. The circuit uses a digital phase-frequency detector (PFD) which provides a wide frequency acquisition capability with NRZ data inputs. An on-chip charge-pump loop filter is used to minimize jitter. The total power consumption is 250mW from 2.5V at 1.6Gb/s.