Darryl R. Freedman, Stanley E. Schuster, et al.
IEEE JSSC
Logic circuits were designed and fabricated in a 1 μm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional “Weinberger” layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
Darryl R. Freedman, Stanley E. Schuster, et al.
IEEE JSSC
Stanley E. Schuster, Barbara Chappell, et al.
IEEE Journal of Solid-State Circuits
Stanley E. Schuster, Richard E. Matick
IEEE Journal of Solid-State Circuits
Terry I. Chappell, Stanley E. Schuster, et al.
IEEE Journal of Solid-State Circuits