Swagath Venkataramani

Title

Principal Research Scientist, AIU Architecture and Compilers

Publications

DyVEDeep: Dynamic Variable Effort Deep Neural Networks
- - Sanjay Ganapathy
  - Swagath Venkataramani
  - et al.
- 2020
- ACM TECS
Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks
- - Xiao Sun
  - Jungwook Choi
  - et al.
- 2019
- NeurIPS 2019
Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems
- - Swagath Venkataramani
  - Vijayalakshmi Srinivasan
  - et al.
- 2019
- HiPC 2019
Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators∗
- - Swagath Venkataramani
  - Jungwook Choi
  - et al.
- 2019
- IISWC 2019
DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator
- - Swagath Venkataramani
  - Jungwook Choi
  - et al.
- 2019
- IEEE Micro
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks
- - Sarada Krithivasan
  - Sanchari Sen
  - et al.
- 2019
- ISLPED 2019
BiScaled-DNN: Quantizing long-tailed datastructures with two scale factors for deep neural networks
- - Shubham Jain
  - Swagath Venkataramani
  - et al.
- 2019
- DAC 2019
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks
- - Sanchari Sen
  - Shubham Jain
  - et al.
- 2019
- IEEE TC
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel
- - Eri Ogawa
  - Kazuaki Ishizaki
  - et al.
- 2019
- COOL CHIPS 2019
Data Subsetting: A Data-Centric Approach to Approximate Computing
- - Younghoon Kim
  - Swagath Venkataramani
  - et al.
- 2019
- DATE 2019

Patents

- 25 Feb 2025
- ES
- 4356236
Reformatting Of Tensors To Provide Sub-tensors
- 25 Feb 2025
- IE
- 4356236
Reformatting Of Tensors To Provide Sub-tensors
- 24 Feb 2025
- US
- 12236338
Single Function To Perform Combined Matrix Multiplication And Bias Add Operations
- 11 Nov 2024
- US
- 12141513
Method To Map Convolutional Layers Of Deep Neural Network On A Plurality Of Processing Elements With Simd Execution Units, Private Memories, And Connected As A 2d Systolic Processor Array
- 15 Oct 2024
- GB
- 2604060
Hybrid Data-model Parallelism For Efficient Deep Learning
- 16 Sep 2024
- US
- 12094525
Multichannel Memory To Augment Local Memory
- 05 Aug 2024
- US
- 12056594
Low Precision Deep Neural Network Enabled By Compensation Instructions
- 08 Jul 2024
- CN
- ZL201980032566.3
Low Precision Deep Neural Network Enabled By Compensation Instructions
- 02 Jun 2024
- JP
- 7497946
Hybrid Data-model Parallelism For Efficient Deep Learning
- 30 Apr 2024
- TW
- I840790
Single Function To Perform Combined Matrix Multiplication And Bias Add Operations

Top collaborators

Alberto Mannari

Software Developer

Xiaodong Cui

Principal Research Scientist

Kaoutar El Maghraoui

Principal Research Scientist and Manager, AIU Spyre Model Enablement, AI Hardware Center